1. Field of the Invention
The present invention relates generally to floating gate flash memory with an asymmetric floating gate and a method of fabricating and operating such a memory.
2. Background of the Invention
There is a continuing desire to improve density of semiconductor devices, especially semiconductor memory devices. In this regard, there have been advances in flash memory, and particularly NAND-type flash memory, providing for higher density, lower cost-per-bit, and higher programming throughput.
Some prior art NAND-type flash memory structures, like that described in U.S. Pat. No. 4,939,690, require shallow junctions that are formed in the surface of a substrate in such a way that the shallow junctions somewhat overlap gates of transistors that overlie the shallow junctions. The shallow junctions serve as source and drain regions for corresponding transistors, and are used as regions from which electrons can be injected, typically through an oxide layer, into corresponding floating gates. Of course, such shallow junctions require additional doping steps in the manufacturing process, and there is a limit to how much such a structure can be reduced in size in an effort to increase the overall density of the device.
This particular prior art NAND-type flash memory structure also exhibits unfavorable floating gate interference. In order to control floating gates through poly wordlines, floating gates are made thick to increase the contact area between the floating gates and the wordlines. When devices are shrunk, spaces between the floating gates are also reduced. Consequently, floating gates are more susceptible to interfering with each other, leading to so-called “floating gate interference”
Another, more recent, NAND-type flash memory technology is described in Hsu et al., “Split-Gate NAND Flash Memory at 120 nm Technology Node Featuring Fast Programming and Erase,” 2004 Symposium on VLSI Technology. This memory structure is characterized by having a split structure in which each memory cell has associated therewith two wordlines that control, respectively, a select gate and a control gate to manipulate (erase, program, read) an associated floating gate.
The above Split-Gate flash memory device relies on capacitive coupling between the floating gate and the wordline. However, the area between the floating gate and the wordline is small. Therefore, the structure described in this reference exhibits a low coupling ratio, which is defined as the capacitance between the floating gate and its control gate divided by the total capacitance of the floating gate to its surrounding environment.
This particular technology operates using hot carrier injection. This type of operation, while it is much faster, consumes more power than Fowler-Nordheim (FN) operation.
Thus, while there have been advances in NAND-type flash memory devices, there is still a need to further improve this technology.